Monday, October 20
Session 1: Architecture I
8:30 - 10:15
Comparing SFMD and SPMD Computation for On-chip Multiprocessing of Intermediate Level IU Algorithms, S. Rehfuss, D. Hammerstrom, Oregon Graduate Institute, full paper
Processor/Memory/Array Size Tradeoffs in the Design of SIMD Arrays, M. Herbordt, A. Anand, O. Kidwai, C. Weems, University of Houston, full paper
A 10 GIPS SIMD Processor for PC-based Real-Time Vision Applications, Y. Fujita, S. Kyo, N. Yamashita, S. Okazaki, NEC Corporation, full paper
The CC/IPP, an MIMD-SIMD Architecture for Image Processing and
Pattern Recognition, P. Jonker and J. Vogelbruch, Delft University
of Technology, short paper
Break 10:15 - 10:45
Session 2: Languages and Environments I
10:45 - 12:00
DAISY: A Distributed Architecture for Intelligent SYstems, A. Chella, V. DiGesu, S. Gaglio, G. Gerardi, et. al., Universita' degli Studi di Palermo, full paper
The C// Data Parallel Language on a Shared Memory Multiprocessor, A. Fatni, D. Houzet, J-L. Basille, Institut National Polytechnique, short paper
A Specific Compilation Scheme for Image Processing Architecture, F. Bodin, H. Essafi, M. Pic, IRISA - Equipe CAPS, short paper
External Loop Unrolling of Image Processing Programs: An Optimal
Register Allocation for RISC Arch, N. Zingirian, M. Maresca, Universita
di Genova, short paper
Luncheon Keynote: ZPL:
Exploiting Program Portability For Better Architecture Design,
Larry Snyder, University of Washington
Session 3: Intelligent Sensors
1:30 - 3:00
Analog Sensor Processing Using Exposure Control: A New Concept for High Speed Image Processing, A. Astrom, E. Astrand, Linkoping University, full paper
A Motion Vision Sensor Architecture with Asynchrounous Self-Signalling Pixels, M. Aria-Estrada, M. Tremblay, D. Pousart, Laval University, full paper
Hardware-Software Aspects of Shift-Register Based NEWS Networks
for the Focal Plane, R. Nguyen, D. Mercier, A. Jullian, T. Bernard,
CTME/GIP, full paper
Break 3:00 - 3:30
Session 4: VLSI I
3:30 - 5:00
VLSI Architecture for Embedded Extraction of Dominant Points on Object Contours, S. Dallaire, M. Tremblay, D. Poussart, Laval University, full paper
A Dedicated Image Processor Exploiting Both Spatial and Instruction-Level Parallelism, A.Broggi, M. Bertozzi, G. Conte, Universita di Parma, full paper
Investigating Real-Time Validation of Real-Time Image Processing
ASICs, I. Kraljic, F. Verdier, G. Quenot, B. Zavidovique, Ecole
Polytechnique de Montreal, full paper
Reception 6:00
Tuesday, October 21
Session 5: Configurable Computing
8:30 - 10:15
FPGA-based Computing in Computer Vision, N. Ratha, A. Jain, IBM Research, full paper
Multilayer Perceptrons on Splash 2, N. Ratha, A. Jain, IBM Research, full paper
Parallel Object Recognition on an FPGA-based Configurable Computing Platform, Y. Chung, S. Choi, and V. Prasanna, University of Southern California, full paper
Real-time Hierarchical Visual Tracking Using a Configurable Computing
Machine, B. Pudipeddi, A. Abbott, P. Athanas, Virginia Polytechnic
Institute and State Univ. , short paper
Break 10:15 - 10:45
Session 6: Languages and Environments II
10:45 - 12:00
Making a Dataparallel Language Portable for SIMD Array Computers, M. Herbordt, J. Burrill, C. Weems, University of Houston, full paper
An Interactive Tool for Computer Vision Tutorials, A. Biancardi, V. Cantoni, D. Codega, M. Pini, Universita di Pavia, short paper
Context: A New Paradigm to Control Distributed Perceptual Systems, V. Di Gesu, F. Isgro, Universita di Palermo, short paper
A Parallelizing Method for Implementing Image Processing Tasks
on SIMD Linear Processor Arays, S. Kyo, S. Okazaki, Y. Fujita,
N. Yamashita, NEC Corparation, short paper
Luncheon Keynote:
Computational Challenges in Aerial
Image Interpretation, Edward Riseman, University of Massachusetts
Session 7: Algorithms
1:45 - 3:00
Hough Transform Implementation on a Reconfigurable Highly Parallel CAM Architecture, M. Meribout, M. Nakanishi, T. Ogura, NTT System Laboratories, full paper
Page Segmentation Using a Pyramidal Architecture, V. Cantoni, L. Cinque, L. Lombardi, G. Manzini, Universita' di Roma La Sapienza, short paper
A Fast Parallel Algorithm for Stereovision, R. Henkel, University of Bremen, short paper
Three Dimensional Graphics Algorithms on the Micro-Grain Array
Processor-II, B. Bishop, Y. Zhang, K. Acken., M.J. Irwin, R.M.
Owens, The Pennsylvania State University, short paper
Break 3:00 - 3:30
Session 8: Novel Approaches
3:30 - 5:00
Design of Highly-Parallel Image Processing Systems using Nanoelectronic Devices, T.J. Fountain, University College London, full paper
Circuital Markov Random FIelds for Analog Edge Detection, M. Storace, M. Parodi, and C. Regazzoni, Universita' degli Studi di Genova, full paper
Image Processing in a Tree of Peano Coded Images, G. Seetharaman, B. Zavidovique, University of Southwestern Louisiana, short paper
Asynchronous SIMD: An Architectural Concept for High Performance
Image Processing, C. Weems, University of Massachusetts, full
paper
Dinner Outing to Boston Museum of
Science 6:30 - 10:30
Wednesday, October 22
Session 9: Architecture II
8:30 - 10:15
Image Processing PCI-based Shared Memory Architecture Design, D. Houzet, A. Fatni, J-L. Basile, Institut National Polytechnique, full paper
A General Purpose SliM-II Image Processor, H. Chang, S. Ong, C. Lee, M. Sunwoo, T. Cho, Ajou University, full paper
The DARPA Image Understanding Motion Benchmark, C. Weems, S. Dropsho., G. Weaver, R. Kumar, J. Burrill, University of Massachusetts, full paper
A Scalable Architecture for Low and Intermediate Level Image Processing,
J. Olk, P. Jonker, Delft University of Technology, short paper
Break 10:15 - 10:45
Session 10: VLSI II
10:45 - 12:00
Vision Chip Architecture Using General-Purpose Processing Elements for a 1 ms Vision System, T. Komuro. I. Ishii, M. Ishikawa, University of Tokyo, short paper
A VLSI Architecture for Real-Time Edge Linking, A. Hajjar, T. Chen, Colorado State University, short paper
A Cost-Effective Morphological Filter Architecture, S. Ong, M. Sunwoo, Ajou University, short paper
A VLSI Architecture for Optimal Correspondence of String Subsequences, N. Ranganathan, R. Motamarri, Univ. of South Florida, short paper
Towards a VHDL-based Synthesis of a Wavelet Transform Processor,
M. Ferretti and D. Rizzo, Universita' degli Studi di Pavia, short
paper
Adjourn 12:00