As CPUs rely increasingly on parallelism rather than frequency to improve performance, the memory system emerges as the fundamental barrier to continued improvement in system-level performance. Previous tactics like increasing cache size and associativity become less and less relevant in a world where NUMA memory behaviors and inter-processor contention dominate application performance. MSPC is a forum for exploring these emerging challenges. This multidisciplinary workshop fosters collaboration among researchers in compilers, programming languages, architecture, operating systems and adjacent specialties. Remember to register for MSPC when you register for ASPLOS!
Final Program

9:00 am - Welcome and Introduction
Emery Berger and Brad Chen

9:30 am - Programming Methodology
Session Chair: Emery Berger, University of Massachusetts Amherst

General and efficient locking without blocking
Yannis Smaragdakis, Anthony Kay, Reimer Behrends and Michal Young
Concurrency Control with Data Coloring
Luis Ceze, Christoph von Praun, Calin Cascaval, Pablo Montesinos and Josep Torrellas

10:30 am - Break
10:45 am - Memory Systems for Parallel Hardware
Session Chair: Trevor Mudge, University of Michigan

The Potential for Variable-Granularity Access Tracking for Optimistic Parallelism
Mihai Burcea, J. Gregory Steffan and Cristiana Amza
Reasoning about the ARM weakly consistent memory model
Nathan Chong and Samin Ishtiaq
IWannaBit!
Cliff Click

12:15 pm - Lunch

1:15 pm - Wild and Crazy Ideas Session

2:15 pm - Software Analysis
Session Chair: Cliff Click, Azul Systems

What can performance counters do for memory subsystem analysis?
Stephane Eranian
The Case for Simple, Visible Cache Coherency
Robert Kunz and Mark Horowitz
GC Assertions: Using the Garbage Collector to Check Heap Properties
Edward Aftandilian and Samuel Guyer

3:45 pm - Break

4:00 pm - Panel: The Next Solution
Session Chair: Bruce Jacob, University of Maryland
People have been complaining about the memory system for at least two decades. As a result, industry and academia have explored numerous solutions, in both software and hardware, at the technology level, the channel level, and the system level. The applications folks have expected big rewards from each solution, only to be disappointed at just about every turn. One of the most recent examples is multicore (one of many "indirect" solutions, marketed as not solving but tolerating the memory system), which exacerbated the memory-bandwidth problem instead of reducing it. Today, people still complain about the memory system: if anything, the problem is commonly represented as getting worse. So what is the next solution?

panel participants

  • Rick Hetherington, Sun
  • Hillery Hunter, IBM Watson
  • Jim Larus, Microsoft
  • Sean Lee, GA Tech
  • Moin Qureshi, IBM
  • Dave Resnick, Micron
  • Scott Rixner, Rice
  • Tim Sherwood, UCSB
  • Pete Vogt, Intel
5:30 pm - Concluding Remarks