Server: Netscape-Enterprise/2.01 Date: Fri, 21 Nov 1997 04:57:51 GMT Accept-ranges: bytes Last-modified: Wed, 15 Oct 1997 18:36:32 GMT Content-length: 5266 Content-type: text/html Dallas Semiconductor Corp: Silicon Timed Circuits (Delay Lines) Design Guide
Dallas Semiconductor Corporation

Silicon Timed Circuits: The Solution for the 90's

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Contents:

What Are Silicon Timed Circuits?
What They Are
Architectures
How Do They Work?
Ramp Generators

General Design
Considerations

Decoupling
Output Loading

Multi-phase
Clock Generator

Skew Correction

Glitch Filters

Pulse Width Modulators/
Programmable One-Shots

Oscillators

Frequency Doublers

Clock Fail Detector

Frequency/Pulse
Width Discriminator

Replacing Active
Hybrid Delays

Replacing Passive
Hybrid Delays

Programmable Delays

Frequently Asked
Questions

Selection Tables

Technical Support

Introduction to This Guide

Delay lines aren't what they used to be. And they're not used like they used to be. Today's Silicon Timed Circuits offer new ways to add functionality to a design, even fine-tune a design and bring it to completion as fast as we're driven to these days. And today's delay lines have moved beyond the "last resort" reputation. We've come a long way from the original hybrid delay lines comprised of coils and capacitors. Those capacitors could introduce inductance and possible ringing into the system. Who wanted to own up to a design with delay lines' bulky "DIP on steroids" packaging? The advent of active hybrids alleviated things somewhat with on-chip buffers isolating the IC delay components, but the bulky packaging and reliability concerns remained.

With the introduction of monolithic silicon delay lines by Dallas Semiconductor, all that changed. Gone was the hybrid implementation, replaced by devices just like any other IC, offering standard IC packaging (including SOICs) and, most importantly, IC reliability levels.

Some of the "delay line stigma" remains as a result of old attitudes. Yet designers are increasingly looking at Dallas' Silicon Timed Circuits to solve design issues quickly and cost-efficiently. Improvement in CAD tools has lessened the need for "band-aids" to hold together ASICs and other system components, a traditional delay line application. Today these devices are finding growing acceptance as an integral part of a new system design. Ironically, this is caused in part by increasing system clock rates which necessitate careful attention to timing tolerances. Better to use a delay line than invoke a wait state! In other instances, delay lines are quite simply the easiest way to achieve a particular design goal.

This Designer's Guide contains an overview of our Silicon Timed Circuits delay line family, gives you insight into their function, and hopefully will give you some ideas about how they can help you with your design tasks.


Silicon Timed Circuits Overview
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